1. Field of the Invention
The present invention relates to the field of digital adders and more specifically to the addition and subtraction of floating point numbers.
2. Related Application
This application relates to copending application Ser. No. 311,296, filed Feb. 14, 1989, and entitled "Prenormalization for a Floating-Point Adder."
3. Prior Art
The heart of any computer or microprocessor is the processor itself. One primary function of any processor is its ability to perform arithmetical or logical operations on various inputs to the processor. Various schemes are known in the prior art to provide arithmetic and logic operations in the processor. One necessary arithmetic function inherent in most processors is its ability to add two numbers. The numerical operation of adding two numbers to derive a sum in a digital processor is well-known in the prior art. Further, the operation of subtracting one number from a second number to derive a difference is also well-known in the prior art. Typically, complement addition is utilized to obtain the subtraction operation in most digital processors.
However, implementing such an operation in a computer or a processor entails the difficulty of using hardware circuitry to provide the sum and/or difference of the two numbers. As processors are reduced to a semiconductor device, i.e. on a silicon chip, additional constraints play a role in determining the best scheme for adding and/or subtracting two numbers. Additionally, improving the speed of the adder is especially important when the adder is on the same integrated circuit chip as other circuits which provide other processing functions, because the time needed to perform the addition provides the dominant delay, rather than the inter-chip communication time. Therefore, any reduction in the computation time of adding/subtracting two numbers significantly improves the speed of the processor.
One of the more efficient and precise techniques of adding and/or subtracting two numbers employs the use of adders to perform floating point operations. In a floating point operation, numbers are represented by an exponent and a mantissa. The mantissa is normalized so that there is one non-zero digit to the left of the decimal (or binary) point. For example, a decimal number 4956.43 would be represented as +4.95643 e+3. In a binary operation which is used in the digital processors, the normalized mantissa will be represented by having a value of 1 as its most significant bit (MSB) followed by the floating point.
In a conventional floating point addition/subtraction scheme known in the prior art, the following steps are typically required to solve the sum/difference of two numbers. During the first step, the exponents of the two source operands are compared and subtracted. In the second step, mantissa alignment is achieved by having the mantissa of the smaller operand right shifted by the exponent difference. In the third step mantissas are added, if addition is to be performed. If subtraction is to be performed, then typically a two's complement addition is performed. In step four, the result is post complemented if the result has a negative value. In the fifth step, leading zero detection is performed, generally by using a leading zero encoder to scan for a number of leading zeros. The result will typically have leading zeros, if in subtracting two source operands the operands are very close to each other in magnitude. In step six, post normalization is achieved by causing the mantissa to be shifted left by the number of leading zeros in order to normalize the obtained mantissa. Generally at the same time, the common exponent will be subtracted by the shifted amount. In step seven, a rounding operation is performed. This step is basically another add operation to round the least significant bit (lsb) of the result. Finally, in step eight, if the rounding operation of step seven results in an overflow, then the mantissa will be shifted right and the exponent of the resultant mantissa will be incremented to compensate for the overflow.
Although various floating-point standards are available, one of the most well-known floating point standard which is widely accepted is the IEEE (Institute of Electrical and Electronic Engineers, Inc.) Binary Floating Point Standard 754. However, in implementing the IEEE 754 floating point standard, the above prior sequence of steps is typically performed in a serial fashion. That is, a given step must wait until a result has been obtained in the previous step before that given step can be executed.
It is appreciated then that any reduction in the total number of clock cycles to perform an addition/subtraction operation will provide a faster processor for performing the addition/subtraction operation.
Further, in the implementation of the IEEE Binary Floating Point Standard 754, a precise rounding requirement for the result is needed. The IEEE 754 standard requires the use of a round bit and a sticky bit when performing floating point operations. The round bit is defined as the bit of the unrounded mantissa result that is one position less significant than the lsb used in the resultant mantissa. The sticky bit is defined as the OR of all of the bits in the unrounded mantissa result less significant than the round bit. The existing prior art implementations require the calculation of all or part of the resultant mantissa before the rounding can be calculated. Additionally, as noted in step eight above, a rounding operation may result in an overflow, requiring the mantissa to be shifted one position to the right. Therefore, a step is needed to determine the rounding action and the addition, and another step is needed to post shift the overflowed result, if any.
Again, it is to be appreciated that if the rounding can be determined before the resultant mantissa is obtained, then the sequence of steps, in terms of clock cycles, and possibly an extra rounding adder, in terms of hardware, can be reduced, thereby increasing the overall speed and performance of the processor.